The present invention relates to an electrically rewritable non-volatile semiconductor memory device and, more particularly, to a flash memory.
An EPROM, which is erasable collectively by ultra-violet, an EEPROM, which is erasable electrically, and a flash memory have been developed in this order as a non-volatile semiconductor memory, and have now become popular. The flash memory excels in high speed serial writing/serial reading, and has a large storage capacity. The mass storage capability in flash memory is progressing at a higher rate than DRAM, because a scale-down in processing rule and a multiple-valued technology (Japanese Laid-open Patent Publication No. 4-119594, Japanese Laid-open Patent Publication No. 10-92186, Japanese Laid-open Patent Publication No. 10-334674) are adopted in the flash memory. Multi-bit data are memorized in a memory cell by the multiple-valued technology.
The multiple-valued technology is explained as following. Generally, one bit data has either xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d that corresponds to one of two states of a memory cell. According to the multiple-valued technology, for example, in the case of two-bit memory, a memory cell may assume one of four states. In addition, the four states correspond to xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d, and xe2x80x9c01xe2x80x9d. Then two-bit data is memorized in a memory cell. Referring to FIG. 15, three reading steps, at which three different word line voltages are applied, are needed to read whole two-bit data in a memory cell.
With regard to flash memory for data storage, the minimum unit of serial writing/serial reading is sector (or page). One section has generally a plurality of memory cells that make an array along a word line for data reading. In this flash memory, one sector includes the control data, which is controlled by controller, and user data. The control data include, for example, a first flag that indicates a bad sector, a second flag that indicates a valid data, data corresponding to writing times in the sector, ECC (Error Correcting Code) data for user data in the sector, etc. Although control data varies with the system used.
In the flash memory, for example, the AND type flash memory with 64 Mbytes, one sector is constructed by data regions of 512 bytes and control regions of 16 bytes. The control data are memorized in the control region. In addition, in the AND type flash memory with 256 Mbytes, one sector is constructed by data regions of 2,048 bytes and control regions of 64 bytes. It takes about 50 usec to read each sector, and it takes about 50 nsec by a byte to transfer data.
It is now made a high-capacity of a memory device by raising memory cell density in the memory device. However, when adjacent memory cells are adjacent to each other, an erroneous reading may happen because interference from the nearby bit line is caused by the capacitance between the adjacent bit lines in the case of reading both adjacent memory cells at the same time. In this case, for example, one reading step may be divided to at least two phases, Phase 0 and Phase 1. It is noted that initial memory cell of memory cell array, which is connected to a word line, is numbered as xe2x80x9c0xe2x80x9d, and the following memory cells are numbered as xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d. In Phase 0, the even-numbered memory cells are read (FIG. 14A). In Phase 1, the odd-numbered memory cells are read (FIG. 14B). Therefore, read error may be prevented because interference from the nearby bit line may be controlled by two phases of reading step.
It is noted that the Japanese Laid-open Patent Publication No. 11-176960 discloses the non-volatile semiconductor memory. The semiconductor memory has a set-up means that makes one bit line of the adjacent two bit lines to pre-charge in pre-charge voltage, and makes it on floating state in NAND cell unit. Then the set-up means makes another bit line in plus charge. However, the semiconductor memory relates to processing to read the certain memory cell.
By the way, in the flash memory, one sector is read together. It may be necessary that the desired data are read as fast as possible. Especially, the control data in memory cell of a sector are needed in the controller initially, so that it is necessary to read the control data at a high speed.
Referring to FIG. 18, in logical layout, for example, a sector has a data region (Y000H-Y7FFH) and a control region (Y800H-Y83FH). FIG. 19 shows the physical layout of memory cell array of a sector. Referring to FIG. 19, however, when the all data are read by two phases (Phase 0, Phase 1), it is necessary that two phases have been performed in order to read even the control data. Therefore, referring to FIG. 20, the data of data region must be read in order to read the control data. Then it takes time of reading one sector to read the control data.
Therefore, it is an object of the present invention to provide a electrically rewritable non-volatile semiconductor memory device, in which the certain data, for example, the control data may be read at a high speed.
In accordance with one aspect of the present invention, there is provided a non-volatile semiconductor memory device including a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a reading means. A plurality of bits are memorized at each memory cell. The plurality of bit lines lie at right angle to the word lines. The reading means is configured to read certain data from every (nxe2x88x921)th (n is an integer that is greater than two) memory cell of a memory cell array connecting to at least a word line. The memory cell exists on the point of intersection with the word line and the bit line. Then data reading and data writing are made by applying the voltage on the word line and the bit line. The non-volatile semiconductor memory device is electrically rewritable.
In another aspect of the present invention, the non-volatile semiconductor memory device may further include a writing means. The writing means can write the certain data into every (nxe2x88x921)th (n is an integer that is greater than two) memory cell of a memory cell array that is connecting to at least a word line.
In a further aspect of the present invention, there is provided a non-volatile semiconductor memory device including a-plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a reading means. A plurality of bits are memorized at each memory cell. The plurality of bit lines lie at right angle to the word lines. The reading means is configured to read certain data from at least one predetermined bit of the plurality of bits corresponding to at least one memory cell of a memory cell array that is connecting to at least a word line. The memory cell exists on the point of intersection with the word line and the bit line. Then data reading and data writing are made by applying the voltage on the word line and the bit line. The non-volatile semiconductor memory device is electrically rewritable.
In another aspect of the present invention, the non-volatile semiconductor memory device may further include a writing means. The writing means is configured to write certain data into said at least one predetermined bit of a certain memory cell of a memory cell array that is connecting to at least a word line.
In a further aspect of the present invention, there is provided a non-volatile semiconductor memory device including a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a reading means. A plurality of bits are memorized at each memory cell. The plurality of bit lines lie at right angle to the word lines. The reading means can read certain data from at least one predetermined bit of every (nxe2x88x921)th (n is an integer that is greater than two) memory cell of a memory cell array that is connecting to at least a word line. The memory cell exists on the point of intersection with the word line and the bit line. Then data reading and data writing are made by applying the voltage on the word line and the bit line. The non-volatile semiconductor memory device is electrically rewritable.
In a still further aspect of the present invention, the non-volatile semiconductor memory device may include a writing means. The writing means can write certain data into at least one predetermined bit of every (nxe2x88x921)th (n is an integer that is greater than two) memory cell of a memory cell array that is connecting to at least a word line.
In a yet further aspect of the present invention, the certain data are read from certain memory cell by the reading means based on a command. The command specifies the starting memory cell and the command is inputted from outside.
In a yet further aspect of the present invention, the certain data are control data regarding to the memory cell array that is connecting to at least a word line.
In a yet further aspect of the present invention, there is provided a system including the non-volatile semiconductor memory device. The data input/output process is performed by the non-volatile semiconductor memory device.
According to the non-volatile semiconductor memory device of this invention, the memory device has a reading means. The reading means can read the certain data from every (nxe2x88x921)th (n is an integer, which is more than two) memory cell, for example, from the even-numbered memory cell in the case of n=3 by Phase 0. Therefore, it may take half time of reading one sector to read the certain data.
According to the non-volatile semiconductor memory device of this invention, the memory device has writing means. The writing means can write the certain data in every (nxe2x88x921)th (n is an integer, which is more than two) memory cell, for example, in even-numbered memory cell in the case of n=3 by Phase 0. Therefore, it may take half time of reading one sector to read the certain data.
According to the non-volatile semiconductor memory device of this invention, the memory device has reading means. The reading means can read the certain data from upper bit of the predetermined memory cell, for example, in upper bit of the predetermined memory cell in the case of two-bit memory by READ 1. Then, for example, regarding with two-bit memory, the certain data may be read by only first reading step of three reading steps, which are needed to decide whole two-bit data. Therefore, it may take one-third time of reading one sector to read the certain data. Moreover, regarding with three-bit memory, the certain data may be read by only first reading step of seven reading steps, which are needed to decide whole three-bit data. Therefore, it may take one-seventh time of reading one sector to read the certain data.
According to the non-volatile semiconductor memory device of this invention, the memory device has writing means. The writing means can write the certain data in upper bit of the predetermined memory cell. Therefore, the certain data may be memorized in upper bit of the predetermined memory cell.
In addition, for example, in regard to the memory, the certain data may be read by only first reading step of three reading steps, which are needed to decide whole two-bit data. Therefore, it may take one-third time of reading one sector to read the certain data. Moreover, regarding with three-bit memory, the certain data may be read by only first reading step of seven reading steps, which are needed to decide whole three-bit data. Therefore, it may take one-seventh time of reading one sector to read the certain data.
According to the non-volatile semiconductor memory device of this invention, the memory device has reading means. The reading means can read the certain data from upper bit of every (nxe2x88x921)th (n is an integer that is more than two) memory cell, for example, from upper bit of even-numbered memory cell in the case of n=3. Then the certain data may be read by Phase 0 of READ 1. Therefore, regarding with two-bit memory, it may take one-sixth time of reading one sector to read the certain data.
According to the non-volatile semiconductor memory device of this invention, the memory device has writing means. The writing means can write the certain data in upper bit of every (nxe2x88x921)th (n is an integer that is more than two) memory cell, for example, in upper bit of even-numbered memory cell in the case of n=3. Therefore, the certain data may be memorized in upper bit of every memory cell. In addition, the memory device has reading means, which can read the certain data by Phase 0 of READ 1. Therefore, regarding with two-bit memory, it may take one-sixth time of reading one sector to read the certain data.
According to the non-volatile semiconductor memory device of this invention, the address of the memory cell for reading the certain data may be changed by inputted command.
According to the non-volatile semiconductor memory device of this invention, the control data, which is needed for controller initially, may be read at high speed.
According to the data memory system of this invention, data input/output with outside may be performed by the non-volatile semiconductor memory device. Therefore, the certain data, for example, the control data may be read at high speed.